The present invention relates to a semiconductor device and, more particularly, to a semiconductor device such as a static random access memory which has a high-resistance element having a high resistance and which is suitable for realizing larger scale integration.
FIG. 1 is a circuit diagram of a static random-access memory cell which is composed of a flip-flop circuit consisting of driver MOS transistors Tr.sub.1 and Tr.sub.2 and load resistors R.sub.1 and R.sub.2, and transfer MOS transistors Tr.sub.3 and Tr.sub.4. The memory cell is selected through a word line 13 and data lines 12 to read out data. The load resistors R.sub.1 and R.sub.2 have a high resistance, i.e., 10.sup.10 to 12.sup.12 .OMEGA.. Such load resistors R.sub.1 and R.sub.2 are provided for the purpose of compensating for leakage current which may flow when the MOS transistors Tr.sub.1 and Tr.sub.2 constituting the flip-flop circuit are at "high" level, thereby supplying a current sufficient to enable a static operation to the drain of each of the MOS transistors Tr.sub.1 and Tr.sub.2, and also for the purpose of reducing the stand-by current in the memory. High-resistance elements having the above-described characteristics have heretofore been formed by employing a polycrystalline silicon film. However, to form high-resistance elements suitable for large scale integration, it is an effective practice to reduce the width of such high-resistance polycrystalline silicon film or reduce the thickness of the film. Reduction in the width of the film owes much to the microfabrication technology, and reduction in the film thickness leads to problems such as an increase in resistance of the interconnection area other than the high-resistance area and undesirable etching of the polycrystalline silicon film in the step of etching contact holes for connection with electrodes of aluminum or the like.
One type of method of reducing the thickness of a polycrystalline silicon film is disclosed in the specification of Japanese Patent Laid-Open No. 210658/1984. More specifically, as shown in FIG. 2 herein, a thick insulator 2 is provided on a P-type semiconductor substrate 1, and a thin polycrystalline silicon film 3 is provided all over the surface of the insulator 2 and formed into a desired pattern by a photolithographic technique. Further, a thick polycrystalline silicon film 4 is provided in a similar manner and covered with an insulator 5, and openings are formed to provide electrodes 6 of aluminum or the like. The present inventors produced a resistor having the structure shown in FIG. 2 and have found the following problems. Namely, although a high resistance is obtained by means of the thin polycrystalline silicon film 3 in the prior art structure shown in FIG. 2, when the thick polycrystalline silicon film 4 at the connection with the aluminum electrodes 6 is etched, the thin polycrystalline silicon film 3, which is an underlayer, is undesirably etched by overetching, which overetching needs to be carried out due to nonuniformity in thickness of the thick polycrystalline silicon film 4 and due to nonuniformity in etching rate within the silicon wafer. More specifically, if it is assumed that the thickness of the thin polycrystalline silicon film 3 is represented by t.sub.1, the thickness of the thick polycrystalline silicon film 4 by t.sub.2, the rate of nonuniformity in film thickness by .alpha., and the rate of nonuniformity in etching rate by .beta., the thin polycrystalline silicon film 3 is completely etched away when the following condition is met: EQU t.sub.1 &lt;.alpha..multidot..beta..multidot.t.sub.2 ( 1)
Even when the following condition is satisfied, i.e., EQU t.sub.1 &gt;.alpha..multidot..beta..multidot.t.sub.2 ( 2)
if the thin polycrystalline silicon film 3 is etched, the nonuniformity in the film thickness further increases to make it difficult to control the film thickness, resulting, disadvantageously, in an increase in variation of resistance.